System and method for executing preamble detection, symbol timing recovery, and frequency offset estimation

ABSTRACT

The present invention describes a method and a system for executing preamble detection, symbol timing recovery, and frequency offset estimation that are applied to a PHS system for executing the preamble symbol detection and timing recovery. The system includes a first absolute value circuit, an average circuit, a multiplier, a sample and accumulate circuit coupled to the multiplier, a second absolute value circuit, a first compare circuit, and a second compare circuit, such that the system with the foregoing structure can detect a preamble symbol by less symbols while performing a timing recovery. The invention also describes a frequency offset computation method and its circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system and a method for executingpreamble detection, symbol timing recovery, and frequency offsetestimation, and more particularly to a system and a method that use lesssymbols to detect preamble symbol with the calculation of performingtiming recovery and frequency offset calculation.

2. Description of the Related Art

In a Japanese personal handyphone system (PHS), the preamble of a bursthas a known format of 0110, and the preamble is provided for thesynchronization of a receiving system, wherein the synchronizationincludes a preamble detection, a symbol timing detection, and afrequency offset computation. However, the length of the preamble isfixed, and thus the number of symbols remained for executing the symboltiming detection and frequency offset computation is very limited, afterthe preamble is detected. A probability of error for executing thetiming detection and the frequency offset computation with a limitednumber of symbols becomes larger, and thus it is not easy to obtainaccurate timing detections and frequency offsets.

In U.S. Pat. No. 5,574,399 entitled “COHERENT PSK DETECTOR NOT REQUIRINGCARRIER RECOVERY” (filed on Oct. 30, 1995 and issued at Nov. 12, 1996),a synchronous PSK detector that does not require a carrier recovery isdisclosed, but such PSK detector has the following shortcomings: 1. Onlyphase data is used for performing the timing recovery; 2. The minimumfrequency offset is not necessary a correct frequency offset in a lowSNR environment, and thus its moving average value will be misledgreatly.

In U.S. Pat. No. 6,038,267 entitled “DIGITAL MODULATOR, MAXIMUM-VALUESELECTOR, AND DIVERSITY RECEIVER” (filed on Jan. 24, 1997 and issued onMar. 14, 2000), a digital modulator maximum-value selector, anddiversity receiver is disclosed, but such digital modulator has thefollowing shortcomings: 1. A large number of symbols are needed forlowering the computational error; 2. Many buffers are needed for storingthe large number of symbols.

In view of the description above, a system and a method for executingpreamble detection, symbol timing recovery, and frequency offsetestimation are needed for detecting the preamble symbols with lesssymbols while performing the timing recovery and frequency offsetcalculation, so as to overcome the foregoing shortcomings of the priorart.

SUMMARY OF THE INVENTION

The primary objective of the present invention is to provide a systemfor executing preamble detection, symbol timing recovery, and frequencyoffset estimation that can use less symbols to detect the preamblesymbol while performing a timing recovery.

Another objective of the present invention is to provide a method forexecuting preamble detection, symbol timing recovery, and frequencyoffset estimation that can use less symbols to detect the preamblesymbol while performing a timing recovery.

A further objective of the present invention is to provide a frequencyoffset computation that can use less symbols to compute its frequencyoffset while reducing its noise power.

To achieve the foregoing objectives, the system for detecting preamblesymbols, and timing recovery applied to a PHS system executes thedetection of preamble symbols and the recovery of the timing andcomprises a first absolute value circuit, coupled to a differentialsignal input end for obtaining an absolute value of amplitude for thedifferential signal, an average circuit coupled to the first absolutevalue circuit for obtaining a moving average amplitude for all absolutevalues of amplitude inputted to the differential signal input end, amultiplier having an end coupled to the differential signal input endand another end coupled to a phase control signal, a sample andaccumulate circuit coupled to the multiplier for generating a pluralityof sampling values after executing the sampling and accumulation of thedifferential signals, a second absolute value circuit coupled to thesample and accumulate circuit for respectively obtaining the absolutevalues of the plurality of sampling values, a first compare circuitcoupled to the second absolute value circuit for finding the maximumabsolute value from the plurality of absolute values, and a secondcompare circuit coupled separately to the average circuit and the firstcompare circuit for executing the comparison of the moving averageamplitude and the maximum absolute value, and if the maximum absolutevalue is larger than the moving average amplitude, then a preambledetection signal will be outputted.

To achieve the foregoing objectives, a method for detecting preamblesymbols and timing recovery in accordance with the present inventioncomprises the steps of: using a N-times sampling frequency to sample aplurality of symbol samples, obtaining the amplitude for each samplingpoint, and then using M sampling points for computing the moving averageamplitudes to obtain a moving average amplitude {tilde over (x)},performing a Z-symbol vector average for N sampling points after eachsampling point is processed by a phase signal, obtaining the amplitudefrom the vector average of the N sampling points, and finding themaximum {tilde over (y)} of the N sample point amplitudes, and if {tildeover (y)}>{tilde over (x)}, then a preamble symbol has been found, andthe sampling point is the optimal symbol timing point, wherein N-timesampling frequency is 5 times, and M is equal to 64 sampling points, andZ is either 16 or 3 symbols.

To achieve the foregoing objectives, a frequency offset computationcircuit in accordance with the present invention comprises an N-symboldelay circuit coupled to a phase signal for delaying the output of thephase signal for N symbols, a first subtractor having an end coupled tothe phase signal and another end coupled to the N-symbol delay circuitfor obtaining a phase difference between the phase signal and the phasesignal after delaying N symbols, a second subtractor having an endcoupled to the first subtractor and another end coupled to a specificphase value for subtracting the specific phase value from the phasedifference outputted from the first subtractor, a phase average circuitcoupled to the second subtractor for executing the accumulation of thephase differences outputted from the second subtractor and computing anaverage value, and a division circuit coupled to the phase averagecircuit for dividing the average value by N to obtain the frequencyoffset of the phase signal.

To achieve the foregoing objectives, a frequency offset computationmethod in accordance with the present invention comprises the steps of:(a) obtaining a phase difference of the plurality of symbols for every Nsymbols; (b) subtracting the specific phase value from the phasedifference value; (c) repeating the aforementioned steps (a) to (b) forn times and accumulating the phase difference; (d) performing an averageof the phase differences; and (e) dividing the average value by N toobtain the frequency offset of the symbol.

To make it easier for our examiner to understand the objectives of theinvention, its structure, innovative features, and performance, we use apreferred embodiment together with the attached drawings for thedetailed description of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a phase change of a transmitted signal ofa general PSK system;

FIG. 2 a is a schematic view of a control frame and data frame of ageneral PSK system;

FIG. 2 b is another schematic view of a control frame and data frame ina general PSK system;

FIG. 3 is a schematic view of a phase change of a transmitted signal ofthe present invention;

FIG. 4 is a schematic view of a phase change track of executing 5-timesampling for the symbol according to a preferred embodiment of thepresent invention;

FIG. 5 is a flow chart of a method for detecting preamble symbol andtiming recovery according to a preferred embodiment of the presentinvention;

FIG. 6 is a schematic block diagram of a system for detecting preamblesymbol and timing recovery according to a preferred embodiment of thepresent invention;

FIG. 7 is a flow chart of a frequency offset computation methodaccording to a preferred embodiment of the present invention;

FIG. 8 is a schematic view of a phase change of each symbol of afrequency offset computation method according to a preferred embodimentof the present invention, if the method includes a phase difference ▾fand the period of the symbol is T; and

FIG. 9 is a schematic block diagram of a frequency offset computationcircuit of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Refer to FIG. 1 for the schematic view of a phase change of atransmitted signal of a general PSK system. A system and a method fordetecting preamble symbol and timing recovery and a frequency offsetcomputation circuit and its method according to the present inventionare applied to a PHS. The modulation method used in the PHS is a π/4DQPSK modulation; the wireless access method is TDMA-TDD; thesensitivity at the 0.01 bit error is −96.46 dBm; the frequency is 1900MHz; and the carrier frequency interval is 300 KHz. The π/4 DQPSKmodulation method is related to the present invention, but the rest areprior arts which will not be described here.

A phase-shift keying (PSK) is a digital modulation system extensivelyused in many wireless communications and the π/4 DQPSK modulating is a90-degree phase difference PSK with a π/4 phase shift, wherein eachsymbol is coded with two bits and acts as the phase shift in thetransmitted carrier signal. The relation between the two bits and thephase shift is described as follows: Bit 00 indicates a π/4 phase shift,bit 01 indicates a 3π/4 phase shift, bit 10 indicates a −π/4 phaseshift, and bit 11 indicates −3π/4 phase shift. Therefore, the phasechange at a receiving end is shown in FIG. 1 after a symbol is modulatedby the foregoing π/4 DQPSK and transmitted. The x-axis I representsphase, and the y-axis Q represents a 90-degree phase-difference. Afterthe receiving end has received several symbols, the phase change diagramis obtained as shown in FIG. 1.

Refer to FIGS. 2 a and 2 b for the schematic views of a control frameand data frame of a general PSK system. In FIG. 2 a, a control frame(also known as a communication frame) of a general PHS system includesthe fields such as a ramp (R), a symbol start (SS), a preamble, an unitword (UW, a specific character), a data, and a cyclic redundancy check(CRC, error detection), wherein the field length of R is 4 bits, and thefield length of SS is 2 bits used for notifying the receiving end aboutthe symbol start, and the field length of preamble is 62 bits used bythe receiving end to carry out a timing synchronization and it has aspecial format of 01100110 . . . , and the field length of UW (specificcharacter) is 32 bits used for representing the type of the controlframe, and the field length of data is 108 bits used for carrying thedata of the control frame, and the field length of CRC (error detection)is 16 bits used for executing the data error detection of the controlframe.

In FIG. 2 b, a tracking frame (also known as a data frame fortransmitting voices) of a general PHS system also includes the fieldssuch as a ramp (R), a symbol start (SS), a preamble, an unit word (UW, aspecific character), a data, and a cyclic redundancy check (CRC, errordetection), wherein the field length of R is 4 bits, and the fieldlength of SS is 2 bits used for notifying the receiving end about thesymbol start, and the field length of preamble is 6 bits used by thereceiving end to carry out a timing synchronization and it has a specialformat of 01100110 . . . , and the field length of UW (specificcharacter) is 16 bits used for representing the type of the controlframe, and the field length of data is 180 bits used for carrying thedata of the control frame, and the field length of CRC (error detection)is 16 bits used for executing the data error detection of the controlframe. The detection of preamble system and timing recovery of theinvention are related to the preamble field, and thus other fields willnot be described here (please refer to the specifications of the PHSsystem).

Refer to FIG. 3 for the schematic view of a phase change of atransmitted signal of the present invention. A system and a method fordetecting preamble symbol and timing recovery according to the presentinvention only use the preamble for carrying out the preamble detectionand symbol timing recovery. As described above, the preamble comes witha specific format of 01100110 . . . , and the receiving end onlyreceives two bit patterns of 0110, wherein the bit 01 indicates a ¾πphase shift and the bit 10 indicates a −π/4 phase shift. Therefore, thephase change as shown in FIG. 3 only jumps between −π/4 and ¾π.

Refer to FIG. 4 for the schematic view of a phase change track ofexecuting 5-time sampling for the symbol according to a preferredembodiment of the present invention. As described above, the prior artsynchronous PSK detector only use the phase data to carry out the timingrecovery, and thus the minimum frequency offset in a low SNR environmentis not necessary a correct frequency offset, and its moving average willbe misled greatly. Besides using the phase data for carrying out thepreamble detection and the timing recovery, the present invention alsouses the amplitude data to overcome the shortcomings of the prior art.In FIG. 4, the method for executing the preamble detection and symboltiming recovery according to the present invention takes a sampling ofthe phase of the preamble including but not limited to a 5-time samplingand its resolution is 1/10 symbols. Therefore, the locus of eachsampling point a, b, c, d, e and its amplitude vector data can be seenduring the process of jumping between −π/4 and ¾π. The amplitude vectordata of each sampling point a, b, c, d, e can determine which samplingpoint has the most powerful energy, and such sampling point is theoptimal symbol sampling point. The related principle and advantages willbe described as followings.

Referring to FIG. 5 for the flow chart of a method for detectingpreamble symbol and timing recovery according to a preferred embodimentof the present invention, the method for detecting preamble symbol andtiming recovery comprises the following steps of: (Step 1) using anN-time sampling frequency to sample a plurality of symbols; (Step 2)obtaining an amplitude for each sampling point, and then using theamplitudes of M sampling points as a moving average amplitude to computea moving average amplitude {tilde over (x)}; (Step 3) computing a vectoraverage for Z symbols of N sampling points, after each sampling point isprocessed by a phase signal; (Step 4) obtaining an amplitude for thevector average of N sampling points and finding a maximum {tilde over(y)} from these N sampling points; and (Step 5) if {tilde over(y)}>{tilde over (x)}, then it indicates that a preamble symbol isfound, and the sampling point is the optimal symbol timing point.

In Step 1, this invention uses an N-time sampling frequency to sample aplurality of symbols, where N is 5, and there are five sampling pointsa, b, c, d, e.

In Step 2, each sampling points a, b, c, d, e obtains its amplitude, andthese amplitudes represent the energy level of the sampling points ofthe symbols. In FIG. 4, the sampling point a has the strongestamplitude, and thus the symbol at the sampling point a has the strongestenergy level, and then the amplitudes of the M sampling points includebut not limited to 64, which are used as the moving average amplitude tocompute a moving average amplitude {tilde over (x)} of the samplingpoints a, b, c, d, e.

In Step 3, after each sampling point is processed by a phase signal, thevector average of five sampling points a, b, c, d, e for Z symbolsincluding but not limited to 16 or 3 symbols is calculated to accumulatethe amplitude of each sampling point a, b, c, d, e of all symbols andobtain the average amplitude for each sampling point. The differencebetween Steps 2 and 3 resides on that Step 2 computes the averageamplitude {tilde over (x)} of the sampling points a, b, c, d, e of allsymbols and Step 3 computes the average amplitudes ã, {tilde over (b)},{tilde over (d)}, {tilde over (e)} of the amplitudes produced by thesampling points a, b, c, d, e of all symbols.

In Step 4, the vector average of five sampling points a, b, c, d, e isused to obtain the amplitudes ã, {tilde over (b)}, {tilde over (d)},{tilde over (e)}, and a maximum {tilde over (y)} is found from the thesefive sampling point amplitudes.

In Step 5, if the sampling point average amplitude {tilde over (y)} inã, {tilde over (b)}, {tilde over (d)}, {tilde over (e)}, and {tilde over(e)} is larger than the average amplitude {tilde over (x)} of allsampling points, then it indicates that a preamble symbol is found, andthe sampling point is an optimal symbol timing. In FIG. 4, if thesampling point has the strongest amplitude, then its average amplitude ãis also the maximum average amplitude in ã, {tilde over (b)}, {tildeover (d)}, {tilde over (e)}, and {tilde over (e)}. Then, Step 5 justneeds to compare the amplitude ã and check if it is larger than theaverage amplitude {tilde over (x)}; if yes, then it indicates that theaforementioned symbol is detected, and the sampling point a is anoptimal symbol timing.

The method of this invention references the phase information as well asthe amplitude information ã, {tilde over (b)}, {tilde over (d)}, {tildeover (e)} of the symbols, and thus the invention can overcome theshortcomings of the prior art. For example, if there is only noise butno signal in a low SNR environment and the noise is a Gaussian whitenoise, then the noise has an even phase distribution, In other words,each phase includes an amplitude distribution. The average amplitude{tilde over (x)} of the power is relatively weaker. If a signal isinputted, the maximum of its amplitude information ã, {tilde over (b)},{tilde over (c)}, {tilde over (d)}, {tilde over (e)} will be larger than{tilde over (x)}, since the sampling points a, b, c, d, e of the symbolshave the same phase. If the maximum of the amplitude information ã,{tilde over (b)}, {tilde over (d)}, {tilde over (e)} is larger than{tilde over (x)}, then there will be an inputted symbol. Therefore, theinvention can detect the preamble of the symbol quickly.

Referring to FIG. 6 for the schematic block diagram of a system fordetecting preamble symbol and timing recovery according to a preferredembodiment of the present invention, the system 1 for detecting preamblesymbols and timing recovery can be applied to a PHS system for executingthe detection of preamble symbols and the recovery of timing recovery.The system 1 comprises a first absolute value circuit 11, an averagecircuit 12, a multiplier 13, a sample and accumulate circuit 14, asecond absolute value circuit 15, a first compare circuit 16, and asecond compare circuit 17.

The first absolute value circuit 11 is coupled to a differential signalinput end for finding an absolute value of amplitude for thedifferential signal, wherein the differential signal input end includesthe input of differential I, Q signals.

The average circuit 12 is coupled to the first absolute value circuit 11for finding a moving average amplitude for all absolute value ofamplitudes inputted from the differential signal input end. Asillustrated in FIG. 5 and described in Step 2, the average amplitude{tilde over (x)} for the sampling points a, b, c, d, e of all symbolscan be found.

The multiplier 13 has an end coupled to the differential signal inputend and another end coupled to a phase control signal (−1)^(n). The n isthe number of incoming symbol, and this phase control signal is 1 and −1alternately.

The sample and accumulate circuit 14 is coupled to the multiplier 13 forexecuting the sampling and accumulation of the differential signals, andthen producing a plurality of sampling values; wherein the sample andaccumulate circuit 14 executes the sampling and accumulation accordingto the following formula:${y_{k} = {\frac{1}{n}{\sum\limits_{i = 1}^{n}x_{{{({i - 1})}*5} + k}}}},$where i is the serial number of input symbol, and k is the number ofsampling point of a symbol, that is k=0,1,2,3,4.

The second absolute value circuit 15 is coupled to the sample andaccumulate circuit 14 for separately obtaining the absolute values ofthe plurality of sampling values. In FIG. 5, Step 3 obtains the absolutevalue of the average amplitude ã, {tilde over (b)}, {tilde over (d)},{tilde over (e)} on the sampling point a, b, c, d, e of all symbols.

The first compare circuit 16 is coupled to the second absolute valuecircuit 15 for obtaining the maximum absolute value from the pluralityof absolute values ã, {tilde over (b)}, {tilde over (d)}, {tilde over(e)}. In addition, the first compare circuit 16 further outputs anoptimal symbol sampling point signal (peak_index) to be used by thefrequency offset computation circuit.

The second compare circuit 17 is coupled separately to the averagecircuit 12 and the first compare circuit 16 for executing the comparisonof the moving average amplitude {tilde over (x)} and the maximumabsolute value of ã, {tilde over (b)}, {tilde over (d)}, {tilde over(e)} and {tilde over (e)}. If the maximum absolute value of ã, {tildeover (b)}, {tilde over (d)}, {tilde over (e)} and {tilde over (e)} islarger than the moving average amplitude {tilde over (x)}, then apreamble detection signal will be outputted.

Therefore, the foregoing structure of the system that can detectpreamble symbol and timing recovery only needs to use less symbols todetect the preamble symbol, and thus can definitely overcome theshortcomings of the prior art.

Referring to FIG. 7 for the flow chart of a frequency offset computationmethod according to a preferred embodiment of the present invention, thealgorithm of the frequency offset computation method of the invention isdescribed as follows:θ_((n+4))−θ_(n)=π+4×Δf×T _(symbol) +n(σ²)  (Formula 1)Shift π and then divide both sides by 4 to obtain the following:Δf×T _(symbol) +n(σ²/4²)= b 1/4 ((θ_(n+4)−θ)−π)  (Formula 2)Compared with the 1-symbol differential frequency offset computationmethod of the prior art, Formula 2 of the invention decreases the noisepower σ to 1/16.

The frequency offset computation method comprises the steps of: (Step 1)obtaining a phase difference value from a plurality of symbols for everyN symbols; (Step 2) subtracting a specific phase value from the phasedifference value; (Step 3) repeating Steps 1 and 2 for n times andaccumulating a phase difference; (Step 4) computing the average of thephase differences; and (Step 5) dividing the average by N to obtain thefrequency offset of the symbol.

In Step 1, the frequency offset computation method of the inventionsamples its phase difference value for every four symbols. Therefore, Nis equal to 4, which means that the phase difference value of the 5^(th)symbol and the 1^(st) symbol is obtained, and the amplitude differencevalue and the phases of the 6^(th) symbol and the 2^(nd) symbol areobtained, and so on. Therefore, the frequency offset computation methodof the invention just needs 12 symbols to obtain the required 8 phasesand amplitude difference value.

In Step 2, it is necessary to subtract specific phase value from thephase difference value. If the frequency difference ▾f is zero and theperiod of the symbol is T, then the phase change of every symbol isshown in FIG. 8. Referring to Table 1, the phase of the 0^(th) symbol is¼π, the phase of the 1^(st) symbol is 0+▾f T, the phase of the 2^(nd)symbol is ¾π+2 ▾f T, the phase of the 3^(rd) symbol is 2/4π+3 ▾f T, andso on. Thus, the phase of the 11^(th) symbol is 2/4π+11 ▾f T. Referringto Table 2, if the phase difference value is the phase difference valuebetween two symbols, the phase of the 0^(th) symbol is 2/4π+2 ▾f T, thephase of the 1^(st) symbol is 2/4π+2 ▾f T, the phase of the 2^(nd)symbol is 2/4π+2 ▾f T, the phase of the 3^(rd) symbol is 2/4π+2 ▾f T,and so on. Therefore, the phase of the 9^(th) symbol is 2/4π+2 ▾f T, andthe specific phase value is 2/4π.

Referring to Table 3, if the phase difference value is a phasedifference value among three symbols, then the phase of the 0^(th)symbol is ¼π+3 ▾f T, the phase of the 1^(st) symbol is 5/4π+3 ▾f T, thephase of the 2^(nd) symbol is ¼π+3 ▾f T, the phase of the 3^(rd) symbolis 5/4π+3 ▾f T, and so on. The phase of the 9^(th) symbol is 5/4π+3 ▾fT, and thus it is necessary to subtract ¼π from all phase differencevalues and then subtract π from the phase difference value of the oddsymbols in this complicated situation.

Referring to Table 4, if the phase difference value is a phasedifference value among four symbols, then the phase of the 0^(th) symbolis π+4 ▾f T, the phase of the 1^(st) symbol is π+4 ▾f T, the phase ofthe 2^(nd) symbol is π+4 ▾f T, the phase of the 3^(rd) symbol is π+4 ▾fT, and so on. The phase of the 9^(th) symbol is π+4 ▾f T. Therefore, thespecific phase value is π.

In Step 3, the foregoing Steps 1 and 2 are repeated for n times, and thephase differences are accumulated, where n is equal to 8 times (asdescribed in Step 1).

In Step 4, the average of the phase differences is obtained.

In Step 5, the average is divided by N to obtain the frequency offset ofthe symbol.

Unlike the prior art, the frequency offset computation method of thepresent invention uses less symbols (8 symbols) to complete thefrequency offset computation, and the noise power σ² is decreased to1/N² which is 1/16.

Referring to FIG. 9 for the schematic block diagram of a frequencyoffset computation circuit of the present invention, the frequencyoffset computation circuit 2 of the invention comprises: an N-symboldelay circuit 21, a first subtractor 22, a second subtractor 23, a phaseaverage circuit 24, and a division circuit 25.

The N-symbol delay circuit 21 is coupled to a phase signal foroutputting a phase signal after the phase signal is delayed for Nsymbols, wherein N is equal to but not limited to 4.

The first subtractor 22 has an end coupled to the phase signal andanother end coupled to the N-symbol delay circuit 21 for obtaining aphase difference between phase signals after the phase signal and thedelayed N symbol are obtained. For example, if N is equal to 4, then thefirst subtractor 22 takes the phase difference value of the 5^(th)symbol and the 1^(st) symbol, the phase difference value of the 6^(th)symbol and the 2^(nd) symbol, and so on. A total of 8 phase differencevalues are obtained.

The second subtractor 23 has an end coupled to the first subtractor 22and another end coupled to a specific phase value for subtracting thespecific phase value from the phase difference outputted from the firstsubtractor 23 due to the frequency constellation. As described above,the specific phase value is ¼π, 2/4π, or π.

The phase average circuit 24 is coupled to the second subtractor 23 forexecuting the accumulation and obtaining the average of the phasedifference values outputted from the second subtractor 23, wherein thenumber of accumulation is 8 times, and the average is obtained afterexecuting the accumulation for 8 times.

The division circuit 25, which is coupled to the phase average circuit24, for dividing the average by N to obtain the frequency offset of thephase signal, wherein N is equal to 4.

The frequency offset computation circuit 2 of the invention furthercomprises a phase buffer 20 coupled to the phase signal and between theN-symbol delay circuit 21 and the first subtractor 22 for storing andmaintaining the phase signal, wherein the phase buffer 20 furtherincludes the input of a phase signal and an optimal symbol samplingpoint signal (peak_index), and the phase buffer 20 starts storing thephase signal when the symbol sampling point signal is not enabled, andstarts outputting the phase required for the frequency estimationaccording to the optimal symbol sampling point. In other words, when thesystem 1 for detecting preamble symbol and timing recovery has detecteda preamble symbol, the optimal symbol sampling point signal starts thefrequency offset computation circuit 2 to execute the frequency offsetcomputation.

Therefore, the foregoing structure of the frequency offset computationcircuit 2 just needs to use less symbols to compute the frequencyoffset, and thus it definitely can overcome the shortcomings of thepresent invention.

With the implementation of the present invention, less symbols are usedfor detecting the preamble symbol while carrying out the timing recoveryand frequency offset computation. The system and method of the inventiondefinitely can overcome the shortcomings of a synchronous PSK detectorof a prior art PHS system.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

1. A method for detecting preamble symbol and timing recovery,comprising the steps of: sampling a plurality of symbols by an N-timesampling frequency; obtaining an amplitude from each sampling point, andusing the amplitude of M sampling points as a moving average amplitudeto compute a moving average amplitude {tilde over (x)}; computing avector average of Z symbols from said N sampling points after said eachsampling point is processed by a phase signal; obtaining an amplitude ofsaid vector average of said N sampling points and computing a maximum{tilde over (y)} from the amplitudes of said N sampling points; and if{tilde over (y)}>{tilde over (x)}, then a preamble symbol is found, andsaid sampling point is an optimal symbol timing.
 2. The method fordetecting preamble symbol and timing recovery of claim 1, wherein saidN-time sampling frequency is 5 times, M is 64 sampling points and Z is16 or 3 symbols.
 3. The method for detecting preamble symbol and timingrecovery of claim 1, wherein said symbol is a symbol of a PHS system. 4.The method for detecting preamble symbol and timing recovery of claim 1,wherein said symbol adopts a π/4 DQPSK modulation method, and saidpreamble symbol adopts a specific format with
 0110. 5. A system fordetecting preamble symbol and timing recovery, being applied in a PHSsystem for executing a detection of preamble symbol and a recovery oftiming, comprising a first absolute value circuit, coupled to adifferential signal input end, for obtaining an absolute value ofamplitude from said differential signal; an average circuit, coupled tosaid first absolute value circuit, for obtaining a moving averageamplitude for all absolute value of amplitudes inputted from saiddifferential signal input end; a multiplier, having an end coupled tosaid differential signal input end and another end coupled to a phasecontrol signal; a sample and accumulate circuit, coupled to saidmultiplier for producing a plurality of sampling values after executinga sampling and an accumulation to said differential signal; a secondabsolute value circuit, coupled to said sample and accumulate circuitfor respectively obtaining absolute values of said plurality of samplingvalues; a first compare circuit, coupled to said second absolute valuecircuit, for obtaining a maximum absolute value from said plurality ofabsolute values; and a second compare circuit, separately coupled tosaid average circuit and said first compare circuit, for executing acomparison of said moving average amplitude and said maximum absolutevalue, and if said maximum absolute value is larger than said movingaverage amplitude, then a preamble detection signal will be outputted.6. The system for detecting preamble symbol and timing recovery of claim5, wherein said differential signals are differential I signal anddifferential Q signal.
 7. The system for detecting preamble symbol andtiming recovery of claim 5, wherein said phase control signal is(−1)^(n), and n is number of the incoming symbol.
 8. The system fordetecting preamble symbol and timing recovery of claim 7, wherein saidsample and accumulate circuit executes said sampling and accumulationaccording to the following formula:${y_{k} = {\frac{1}{n}{\sum\limits_{i = 1}^{n}x_{{{({i - 1})}*5} + k}}}},$where i is a serial number of input symbol, and k is the number ofsampling point of a symbol, that is k=0,1,2,3,4.
 9. The system fordetecting preamble symbol and timing recovery of claim 5, wherein saidfirst compare circuit further outputs an optimal symbol sampling pointsignal.
 10. A frequency offset computation method, comprising the stepsof: (a) obtaining a phase difference value from a plurality of symbolsfor every N; (b) subtracting a specific phase value from said phasedifference value; (c) repeating steps (a) to (b) for n times andaccumulating a phase difference; (d) computing an average from saidphase differences; and (e) dividing said average by N to obtain afrequency offset of said symbol.
 11. The frequency offset computationmethod of claim 10, wherein said N is equal to
 4. 12. The frequencyoffset computation method of claim 11, wherein a total number of saidsymbol is 12, and n is equal to
 8. 13. The frequency offset computationmethod of claim 11, wherein said specific phase value is equal to 2/4πif said phase difference value is a phase difference value of twosymbols.
 14. The frequency offset computation method of claim 11,wherein if said phase difference value is a phase difference value withthree symbols, it is necessary to subtract ¼π from all phase differencevalues and then subtract π from the phase difference value with the oddsymbols.
 15. The frequency offset computation method of claim 11,wherein said specific phase value is equal to π if said phase differencevalue is a phase difference value of four symbols.
 16. A frequencyoffset computation circuit, comprising: an N-symbol delay circuit,coupled to a phase signal for outputting said phase signal after Nsymbols are delayed; a first subtractor, having an end coupled to saidphase signal and another end coupled to said N-symbol delay circuit, forobtaining a phase difference between said phase signal and said phasesignal after being delayed for N symbols; a second subtractor, having anend coupled to said first subtractor and another end coupled to aspecific phase value, for subtracting a specific phase value from saidphase difference outputted from said first subtractor; a phase averagecircuit, coupled to said second subtractor, for executing anaccumulation and computing an average for said phase differencesoutputted from said second subtractor; and a division circuit, coupledto said phase average circuit for obtaining said frequency offset ofsaid phase signal after dividing said average by N.
 17. The frequencyoffset computation circuit of claim 16, wherein N is equal to
 4. 18. Thefrequency offset computation circuit of claim 16, wherein a total numberof said symbol is 12, and N is equal to
 8. 19. The frequency offsetcomputation circuit of claim 16, wherein said noise power is decreasedto its original 1/N².
 20. The frequency offset computation circuit ofclaim 16, further comprising a phase buffer coupled to said phase signaland between said N-symbol delay circuit and first subtractor, forstoring said phase signal, wherein said phase buffer further includes aphase signal and an optimal symbol sampling point signal.
 21. Thefrequency offset computation circuit of claim 20, wherein said phasebuffer starts storing said phase signal when said optimal symbolsampling point signal is not enabled and obtaining a phase signal usedfor frequency estimation by said optimal symbol sampling point.
 22. Thefrequency offset computation method of claim 16, wherein said specificphase value is equal to 2/4π if said phase difference value is a phasedifference value of two symbols.
 23. The frequency offset computationmethod of claim 16, wherein if said phase difference value is a phasedifference value with three symbols, it is necessary to subtract ¼π fromall phase difference values and then subtract π from the phasedifference value with the odd symbols.
 24. The frequency offsetcomputation method of claim 16, wherein said specific phase value isequal to π if said phase difference value is a phase difference value offour symbols.